/* Copyright (C) 2018 Red Hat
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */

#ifndef _NIR_INTRINSICS_
#define _NIR_INTRINSICS_



typedef enum {
   nir_intrinsic_accept_ray_intersection,
   nir_intrinsic_addr_mode_is,
   nir_intrinsic_al2p_nv,
   nir_intrinsic_ald_nv,
   nir_intrinsic_alpha_to_coverage,
   nir_intrinsic_alphatst_pco,
   nir_intrinsic_as_uniform,
   nir_intrinsic_ast_nv,
   nir_intrinsic_atest_pan,
   nir_intrinsic_atomic_add_gen_prim_count_amd,
   nir_intrinsic_atomic_add_gs_emit_prim_count_amd,
   nir_intrinsic_atomic_add_shader_invocation_count_amd,
   nir_intrinsic_atomic_add_xfb_prim_count_amd,
   nir_intrinsic_atomic_counter_add,
   nir_intrinsic_atomic_counter_add_deref,
   nir_intrinsic_atomic_counter_and,
   nir_intrinsic_atomic_counter_and_deref,
   nir_intrinsic_atomic_counter_comp_swap,
   nir_intrinsic_atomic_counter_comp_swap_deref,
   nir_intrinsic_atomic_counter_exchange,
   nir_intrinsic_atomic_counter_exchange_deref,
   nir_intrinsic_atomic_counter_inc,
   nir_intrinsic_atomic_counter_inc_deref,
   nir_intrinsic_atomic_counter_max,
   nir_intrinsic_atomic_counter_max_deref,
   nir_intrinsic_atomic_counter_min,
   nir_intrinsic_atomic_counter_min_deref,
   nir_intrinsic_atomic_counter_or,
   nir_intrinsic_atomic_counter_or_deref,
   nir_intrinsic_atomic_counter_post_dec,
   nir_intrinsic_atomic_counter_post_dec_deref,
   nir_intrinsic_atomic_counter_pre_dec,
   nir_intrinsic_atomic_counter_pre_dec_deref,
   nir_intrinsic_atomic_counter_read,
   nir_intrinsic_atomic_counter_read_deref,
   nir_intrinsic_atomic_counter_xor,
   nir_intrinsic_atomic_counter_xor_deref,
   nir_intrinsic_ballot,
   nir_intrinsic_ballot_bit_count_exclusive,
   nir_intrinsic_ballot_bit_count_inclusive,
   nir_intrinsic_ballot_bit_count_reduce,
   nir_intrinsic_ballot_bitfield_extract,
   nir_intrinsic_ballot_find_lsb,
   nir_intrinsic_ballot_find_msb,
   nir_intrinsic_ballot_relaxed,
   nir_intrinsic_bar_break_nv,
   nir_intrinsic_bar_set_nv,
   nir_intrinsic_bar_sync_nv,
   nir_intrinsic_barrier,
   nir_intrinsic_begin_invocation_interlock,
   nir_intrinsic_bindgen_return,
   nir_intrinsic_bindless_image_agx,
   nir_intrinsic_bindless_image_atomic,
   nir_intrinsic_bindless_image_atomic_swap,
   nir_intrinsic_bindless_image_descriptor_amd,
   nir_intrinsic_bindless_image_format,
   nir_intrinsic_bindless_image_fragment_mask_load_amd,
   nir_intrinsic_bindless_image_levels,
   nir_intrinsic_bindless_image_load,
   nir_intrinsic_bindless_image_load_raw_intel,
   nir_intrinsic_bindless_image_order,
   nir_intrinsic_bindless_image_samples,
   nir_intrinsic_bindless_image_samples_identical,
   nir_intrinsic_bindless_image_size,
   nir_intrinsic_bindless_image_sparse_load,
   nir_intrinsic_bindless_image_store,
   nir_intrinsic_bindless_image_store_block_agx,
   nir_intrinsic_bindless_image_store_raw_intel,
   nir_intrinsic_bindless_image_texel_address,
   nir_intrinsic_bindless_resource_ir3,
   nir_intrinsic_bindless_sampler_agx,
   nir_intrinsic_blend2_pan,
   nir_intrinsic_blend_pan,
   nir_intrinsic_blend_return_pan,
   nir_intrinsic_brcst_active_ir3,
   nir_intrinsic_btd_retire_intel,
   nir_intrinsic_btd_spawn_intel,
   nir_intrinsic_btd_stack_push_intel,
   nir_intrinsic_bvh64_intersect_ray_amd,
   nir_intrinsic_bvh8_intersect_ray_amd,
   nir_intrinsic_bvh_stack_rtn_amd,
   nir_intrinsic_cmat_binary_op,
   nir_intrinsic_cmat_bitcast,
   nir_intrinsic_cmat_construct,
   nir_intrinsic_cmat_convert,
   nir_intrinsic_cmat_copy,
   nir_intrinsic_cmat_extract,
   nir_intrinsic_cmat_insert,
   nir_intrinsic_cmat_length,
   nir_intrinsic_cmat_load,
   nir_intrinsic_cmat_load_shared_nv,
   nir_intrinsic_cmat_mov_transpose_nv,
   nir_intrinsic_cmat_muladd,
   nir_intrinsic_cmat_muladd_amd,
   nir_intrinsic_cmat_muladd_nv,
   nir_intrinsic_cmat_scalar_op,
   nir_intrinsic_cmat_store,
   nir_intrinsic_cmat_transpose,
   nir_intrinsic_cmat_unary_op,
   nir_intrinsic_convert_alu_types,
   nir_intrinsic_convert_cmat_intel,
   nir_intrinsic_copy_deref,
   nir_intrinsic_copy_fs_outputs_nv,
   nir_intrinsic_copy_global_to_uniform_ir3,
   nir_intrinsic_copy_push_const_to_uniform_ir3,
   nir_intrinsic_copy_ubo_to_uniform_ir3,
   nir_intrinsic_ddx,
   nir_intrinsic_ddx_coarse,
   nir_intrinsic_ddx_fine,
   nir_intrinsic_ddy,
   nir_intrinsic_ddy_coarse,
   nir_intrinsic_ddy_fine,
   nir_intrinsic_debug_break,
   nir_intrinsic_decl_reg,
   nir_intrinsic_demote,
   nir_intrinsic_demote_if,
   nir_intrinsic_demote_samples,
   nir_intrinsic_deref_atomic,
   nir_intrinsic_deref_atomic_swap,
   nir_intrinsic_deref_buffer_array_length,
   nir_intrinsic_deref_implicit_array_length,
   nir_intrinsic_deref_mode_is,
   nir_intrinsic_deref_texture_src,
   nir_intrinsic_dma_ld_pco,
   nir_intrinsic_dma_ld_shregs_pco,
   nir_intrinsic_dma_st_pco,
   nir_intrinsic_dma_st_shregs_pco,
   nir_intrinsic_dma_st_tiled_pco,
   nir_intrinsic_doorbell_agx,
   nir_intrinsic_dpas_intel,
   nir_intrinsic_dpp16_shift_amd,
   nir_intrinsic_dummy_load_store_pco,
   nir_intrinsic_elect,
   nir_intrinsic_elect_any_ir3,
   nir_intrinsic_emit_primitive_poly,
   nir_intrinsic_emit_vertex,
   nir_intrinsic_emit_vertex_nv,
   nir_intrinsic_emit_vertex_with_counter,
   nir_intrinsic_emitpix_pco,
   nir_intrinsic_end_invocation_interlock,
   nir_intrinsic_end_primitive,
   nir_intrinsic_end_primitive_nv,
   nir_intrinsic_end_primitive_with_counter,
   nir_intrinsic_enqueue_node_payloads,
   nir_intrinsic_exclusive_scan,
   nir_intrinsic_exclusive_scan_clusters_ir3,
   nir_intrinsic_execute_callable,
   nir_intrinsic_execute_closest_hit_amd,
   nir_intrinsic_execute_miss_amd,
   nir_intrinsic_export_agx,
   nir_intrinsic_export_amd,
   nir_intrinsic_export_dual_src_blend_amd,
   nir_intrinsic_export_row_amd,
   nir_intrinsic_fence_helper_exit_agx,
   nir_intrinsic_fence_mem_to_tex_agx,
   nir_intrinsic_fence_pbe_to_tex_agx,
   nir_intrinsic_fence_pbe_to_tex_pixel_agx,
   nir_intrinsic_final_primitive_nv,
   nir_intrinsic_finalize_incoming_node_payload,
   nir_intrinsic_first_invocation,
   nir_intrinsic_flush_tile_buffer_pco,
   nir_intrinsic_frag_store_pco,
   nir_intrinsic_fs_out_nv,
   nir_intrinsic_gds_atomic_add_amd,
   nir_intrinsic_get_ssbo_size,
   nir_intrinsic_get_ubo_size,
   nir_intrinsic_global_atomic,
   nir_intrinsic_global_atomic_2x32,
   nir_intrinsic_global_atomic_agx,
   nir_intrinsic_global_atomic_amd,
   nir_intrinsic_global_atomic_nv,
   nir_intrinsic_global_atomic_pco,
   nir_intrinsic_global_atomic_swap,
   nir_intrinsic_global_atomic_swap_2x32,
   nir_intrinsic_global_atomic_swap_agx,
   nir_intrinsic_global_atomic_swap_amd,
   nir_intrinsic_global_atomic_swap_nv,
   nir_intrinsic_global_atomic_swap_pco,
   nir_intrinsic_ignore_ray_intersection,
   nir_intrinsic_imadsp_nv,
   nir_intrinsic_image_atomic,
   nir_intrinsic_image_atomic_swap,
   nir_intrinsic_image_deref_atomic,
   nir_intrinsic_image_deref_atomic_swap,
   nir_intrinsic_image_deref_descriptor_amd,
   nir_intrinsic_image_deref_format,
   nir_intrinsic_image_deref_fragment_mask_load_amd,
   nir_intrinsic_image_deref_levels,
   nir_intrinsic_image_deref_load,
   nir_intrinsic_image_deref_load_info_nv,
   nir_intrinsic_image_deref_load_param_intel,
   nir_intrinsic_image_deref_load_raw_intel,
   nir_intrinsic_image_deref_order,
   nir_intrinsic_image_deref_samples,
   nir_intrinsic_image_deref_samples_identical,
   nir_intrinsic_image_deref_size,
   nir_intrinsic_image_deref_sparse_load,
   nir_intrinsic_image_deref_store,
   nir_intrinsic_image_deref_store_block_agx,
   nir_intrinsic_image_deref_store_raw_intel,
   nir_intrinsic_image_deref_texel_address,
   nir_intrinsic_image_descriptor_amd,
   nir_intrinsic_image_format,
   nir_intrinsic_image_fragment_mask_load_amd,
   nir_intrinsic_image_heap_atomic,
   nir_intrinsic_image_heap_atomic_swap,
   nir_intrinsic_image_heap_descriptor_amd,
   nir_intrinsic_image_heap_format,
   nir_intrinsic_image_heap_fragment_mask_load_amd,
   nir_intrinsic_image_heap_levels,
   nir_intrinsic_image_heap_load,
   nir_intrinsic_image_heap_load_param_intel,
   nir_intrinsic_image_heap_load_raw_intel,
   nir_intrinsic_image_heap_order,
   nir_intrinsic_image_heap_samples,
   nir_intrinsic_image_heap_samples_identical,
   nir_intrinsic_image_heap_size,
   nir_intrinsic_image_heap_sparse_load,
   nir_intrinsic_image_heap_store,
   nir_intrinsic_image_heap_store_block_agx,
   nir_intrinsic_image_heap_store_raw_intel,
   nir_intrinsic_image_heap_texel_address,
   nir_intrinsic_image_levels,
   nir_intrinsic_image_load,
   nir_intrinsic_image_load_raw_intel,
   nir_intrinsic_image_order,
   nir_intrinsic_image_samples,
   nir_intrinsic_image_samples_identical,
   nir_intrinsic_image_size,
   nir_intrinsic_image_sparse_load,
   nir_intrinsic_image_store,
   nir_intrinsic_image_store_block_agx,
   nir_intrinsic_image_store_raw_intel,
   nir_intrinsic_image_texel_address,
   nir_intrinsic_inclusive_scan,
   nir_intrinsic_inclusive_scan_clusters_ir3,
   nir_intrinsic_initialize_node_payloads,
   nir_intrinsic_interp_deref_at_centroid,
   nir_intrinsic_interp_deref_at_offset,
   nir_intrinsic_interp_deref_at_sample,
   nir_intrinsic_interp_deref_at_vertex,
   nir_intrinsic_inverse_ballot,
   nir_intrinsic_ipa_nv,
   nir_intrinsic_is_helper_invocation,
   nir_intrinsic_is_null_descriptor,
   nir_intrinsic_is_sparse_resident_zink,
   nir_intrinsic_is_sparse_texels_resident,
   nir_intrinsic_is_subgroup_invocation_lt_amd,
   nir_intrinsic_isberd_nv,
   nir_intrinsic_isbewr_nv,
   nir_intrinsic_isp_feedback_pco,
   nir_intrinsic_lane_permute_16_amd,
   nir_intrinsic_last_invocation,
   nir_intrinsic_launch_mesh_workgroups,
   nir_intrinsic_launch_mesh_workgroups_with_payload_deref,
   nir_intrinsic_ldc_nv,
   nir_intrinsic_ldcx_nv,
   nir_intrinsic_ldtram_nv,
   nir_intrinsic_lea_attr_pan,
   nir_intrinsic_lea_buf_pan,
   nir_intrinsic_load_aa_line_width,
   nir_intrinsic_load_accel_struct_amd,
   nir_intrinsic_load_active_samples_agx,
   nir_intrinsic_load_active_subgroup_count_agx,
   nir_intrinsic_load_active_subgroup_invocation_agx,
   nir_intrinsic_load_agx,
   nir_intrinsic_load_alpha_reference_amd,
   nir_intrinsic_load_alpha_to_coverage_enable_ir3,
   nir_intrinsic_load_amplification_id_kk,
   nir_intrinsic_load_api_sample_mask_agx,
   nir_intrinsic_load_attrib_clamp_agx,
   nir_intrinsic_load_attribute_pan,
   nir_intrinsic_load_attribute_payload_intel,
   nir_intrinsic_load_back_face_agx,
   nir_intrinsic_load_barycentric_at_offset,
   nir_intrinsic_load_barycentric_at_offset_nv,
   nir_intrinsic_load_barycentric_at_sample,
   nir_intrinsic_load_barycentric_centroid,
   nir_intrinsic_load_barycentric_coord_at_offset,
   nir_intrinsic_load_barycentric_coord_at_sample,
   nir_intrinsic_load_barycentric_coord_centroid,
   nir_intrinsic_load_barycentric_coord_pixel,
   nir_intrinsic_load_barycentric_coord_sample,
   nir_intrinsic_load_barycentric_model,
   nir_intrinsic_load_barycentric_optimize_amd,
   nir_intrinsic_load_barycentric_pixel,
   nir_intrinsic_load_barycentric_sample,
   nir_intrinsic_load_base_global_invocation_id,
   nir_intrinsic_load_base_instance,
   nir_intrinsic_load_base_vertex,
   nir_intrinsic_load_base_workgroup_id,
   nir_intrinsic_load_blend_const_color_a_float,
   nir_intrinsic_load_blend_const_color_aaaa8888_unorm,
   nir_intrinsic_load_blend_const_color_b_float,
   nir_intrinsic_load_blend_const_color_g_float,
   nir_intrinsic_load_blend_const_color_r_float,
   nir_intrinsic_load_blend_const_color_rgba,
   nir_intrinsic_load_blend_const_color_rgba8888_unorm,
   nir_intrinsic_load_blend_descriptor_pan,
   nir_intrinsic_load_blend_input_pan,
   nir_intrinsic_load_btd_global_arg_addr_intel,
   nir_intrinsic_load_btd_local_arg_addr_intel,
   nir_intrinsic_load_btd_resume_sbt_addr_intel,
   nir_intrinsic_load_btd_shader_type_intel,
   nir_intrinsic_load_btd_stack_id_intel,
   nir_intrinsic_load_buffer_amd,
   nir_intrinsic_load_buffer_ptr_deref,
   nir_intrinsic_load_buffer_ptr_kk,
   nir_intrinsic_load_call_return_address_amd,
   nir_intrinsic_load_callable_sbt_addr_intel,
   nir_intrinsic_load_callable_sbt_stride_intel,
   nir_intrinsic_load_clamp_vertex_color_amd,
   nir_intrinsic_load_clear_value_pan,
   nir_intrinsic_load_clip_half_line_width_amd,
   nir_intrinsic_load_clip_z_coeff_agx,
   nir_intrinsic_load_coalesced_input_count,
   nir_intrinsic_load_coeff_pco,
   nir_intrinsic_load_coefficients_agx,
   nir_intrinsic_load_color0_amd,
   nir_intrinsic_load_color1_amd,
   nir_intrinsic_load_const_buf_base_addr_lvp,
   nir_intrinsic_load_const_ir3,
   nir_intrinsic_load_constant,
   nir_intrinsic_load_constant_agx,
   nir_intrinsic_load_constant_base_ptr,
   nir_intrinsic_load_core_count_arm,
   nir_intrinsic_load_core_id,
   nir_intrinsic_load_core_max_id_arm,
   nir_intrinsic_load_cull_any_enabled_amd,
   nir_intrinsic_load_cull_back_face_enabled_amd,
   nir_intrinsic_load_cull_ccw_amd,
   nir_intrinsic_load_cull_front_face_enabled_amd,
   nir_intrinsic_load_cull_line_viewport_xy_scale_and_offset_amd,
   nir_intrinsic_load_cull_mask,
   nir_intrinsic_load_cull_mask_and_flags_amd,
   nir_intrinsic_load_cull_small_line_precision_amd,
   nir_intrinsic_load_cull_small_lines_enabled_amd,
   nir_intrinsic_load_cull_small_triangle_precision_amd,
   nir_intrinsic_load_cull_small_triangles_enabled_amd,
   nir_intrinsic_load_cull_triangle_viewport_xy_scale_and_offset_amd,
   nir_intrinsic_load_cumulative_coverage_pan,
   nir_intrinsic_load_debug_log_desc_amd,
   nir_intrinsic_load_depth_never_agx,
   nir_intrinsic_load_depth_texture_kk,
   nir_intrinsic_load_deref,
   nir_intrinsic_load_deref_block_intel,
   nir_intrinsic_load_descriptor_set_agx,
   nir_intrinsic_load_draw_id,
   nir_intrinsic_load_esgs_vertex_stride_amd,
   nir_intrinsic_load_exported_agx,
   nir_intrinsic_load_face_ccw_pco,
   nir_intrinsic_load_fb_layers_v3d,
   nir_intrinsic_load_fb_render_area_pan,
   nir_intrinsic_load_fbfetch_image_desc_amd,
   nir_intrinsic_load_fbfetch_image_fmask_desc_amd,
   nir_intrinsic_load_fep_w_v3d,
   nir_intrinsic_load_first_vertex,
   nir_intrinsic_load_fixed_point_size_agx,
   nir_intrinsic_load_flat_mask,
   nir_intrinsic_load_force_vrs_rates_amd,
   nir_intrinsic_load_frag_coord,
   nir_intrinsic_load_frag_coord_gmem_ir3,
   nir_intrinsic_load_frag_coord_unscaled_ir3,
   nir_intrinsic_load_frag_coord_w,
   nir_intrinsic_load_frag_coord_w_rcp,
   nir_intrinsic_load_frag_coord_z,
   nir_intrinsic_load_frag_invocation_count,
   nir_intrinsic_load_frag_offset_ir3,
   nir_intrinsic_load_frag_shading_rate,
   nir_intrinsic_load_frag_size,
   nir_intrinsic_load_frag_size_ir3,
   nir_intrinsic_load_from_texture_handle_agx,
   nir_intrinsic_load_front_face,
   nir_intrinsic_load_front_face_fsign,
   nir_intrinsic_load_front_face_op_pco,
   nir_intrinsic_load_fs_coeffs_pco,
   nir_intrinsic_load_fs_config_intel,
   nir_intrinsic_load_fs_input_interp_deltas,
   nir_intrinsic_load_fs_meta_pco,
   nir_intrinsic_load_fs_start_intel,
   nir_intrinsic_load_fs_z_c0_intel,
   nir_intrinsic_load_fs_z_c_intel,
   nir_intrinsic_load_fully_covered,
   nir_intrinsic_load_geometry_param_buffer_poly,
   nir_intrinsic_load_global,
   nir_intrinsic_load_global_2x32,
   nir_intrinsic_load_global_amd,
   nir_intrinsic_load_global_base_ptr,
   nir_intrinsic_load_global_block_intel,
   nir_intrinsic_load_global_bounded,
   nir_intrinsic_load_global_constant,
   nir_intrinsic_load_global_constant_bounded,
   nir_intrinsic_load_global_constant_offset,
   nir_intrinsic_load_global_constant_uniform_block_intel,
   nir_intrinsic_load_global_cvt_pan,
   nir_intrinsic_load_global_etna,
   nir_intrinsic_load_global_invocation_id,
   nir_intrinsic_load_global_invocation_index,
   nir_intrinsic_load_global_ir3,
   nir_intrinsic_load_global_nv,
   nir_intrinsic_load_global_size,
   nir_intrinsic_load_gmem_frag_offset_ir3,
   nir_intrinsic_load_gmem_frag_scale_ir3,
   nir_intrinsic_load_gs_header_ir3,
   nir_intrinsic_load_gs_vertex_offset_amd,
   nir_intrinsic_load_gs_wave_id_amd,
   nir_intrinsic_load_heap_descriptor,
   nir_intrinsic_load_helper_arg_hi_agx,
   nir_intrinsic_load_helper_arg_lo_agx,
   nir_intrinsic_load_helper_invocation,
   nir_intrinsic_load_helper_op_id_agx,
   nir_intrinsic_load_hit_attrib_amd,
   nir_intrinsic_load_hs_out_patch_data_offset_amd,
   nir_intrinsic_load_hs_patch_stride_ir3,
   nir_intrinsic_load_idvs_output_buf_index_pan,
   nir_intrinsic_load_incoming_ray_payload_amd,
   nir_intrinsic_load_index_size_poly,
   nir_intrinsic_load_indirect_address_intel,
   nir_intrinsic_load_initial_edgeflags_amd,
   nir_intrinsic_load_inline_data_intel,
   nir_intrinsic_load_input,
   nir_intrinsic_load_input_attachment_conv_pan,
   nir_intrinsic_load_input_attachment_coord,
   nir_intrinsic_load_input_attachment_target_pan,
   nir_intrinsic_load_input_topology_poly,
   nir_intrinsic_load_input_vertex,
   nir_intrinsic_load_instance_id,
   nir_intrinsic_load_instance_num_pco,
   nir_intrinsic_load_interpolated_input,
   nir_intrinsic_load_intersection_opaque_amd,
   nir_intrinsic_load_invocation_id,
   nir_intrinsic_load_is_first_fan_agx,
   nir_intrinsic_load_is_indexed_draw,
   nir_intrinsic_load_kernel_input,
   nir_intrinsic_load_layer_id,
   nir_intrinsic_load_lds_ngg_gs_out_vertex_base_amd,
   nir_intrinsic_load_leaf_opaque_intel,
   nir_intrinsic_load_leaf_procedural_intel,
   nir_intrinsic_load_line_coord,
   nir_intrinsic_load_line_width,
   nir_intrinsic_load_local_invocation_id,
   nir_intrinsic_load_local_invocation_index,
   nir_intrinsic_load_local_invocation_index_intel,
   nir_intrinsic_load_local_pixel_agx,
   nir_intrinsic_load_local_shared_r600,
   nir_intrinsic_load_lshs_vertex_stride_amd,
   nir_intrinsic_load_max_polygon_intel,
   nir_intrinsic_load_merged_wave_info_amd,
   nir_intrinsic_load_mesh_view_count,
   nir_intrinsic_load_mesh_view_indices,
   nir_intrinsic_load_multisampled_pan,
   nir_intrinsic_load_noperspective_varyings_pan,
   nir_intrinsic_load_num_subgroups,
   nir_intrinsic_load_num_vertices,
   nir_intrinsic_load_num_vertices_per_primitive_amd,
   nir_intrinsic_load_num_workgroups,
   nir_intrinsic_load_ordered_id_amd,
   nir_intrinsic_load_outgoing_ray_payload_amd,
   nir_intrinsic_load_output,
   nir_intrinsic_load_packed_passthrough_primitive_amd,
   nir_intrinsic_load_packed_sample_location_pco,
   nir_intrinsic_load_param,
   nir_intrinsic_load_patch_vertices_in,
   nir_intrinsic_load_per_primitive_input,
   nir_intrinsic_load_per_primitive_output,
   nir_intrinsic_load_per_primitive_remap_intel,
   nir_intrinsic_load_per_vertex_input,
   nir_intrinsic_load_per_vertex_output,
   nir_intrinsic_load_per_view_output,
   nir_intrinsic_load_persp_center_rhw_ir3,
   nir_intrinsic_load_pipeline_stat_query_enabled_amd,
   nir_intrinsic_load_pixel_coord,
   nir_intrinsic_load_pixel_coord_intel,
   nir_intrinsic_load_pixel_local,
   nir_intrinsic_load_point_coord,
   nir_intrinsic_load_point_coord_maybe_flipped,
   nir_intrinsic_load_poly_line_smooth_enabled,
   nir_intrinsic_load_polygon_stipple_agx,
   nir_intrinsic_load_polygon_stipple_buffer_amd,
   nir_intrinsic_load_preamble,
   nir_intrinsic_load_prim_gen_query_enabled_amd,
   nir_intrinsic_load_prim_xfb_query_enabled_amd,
   nir_intrinsic_load_primitive_id,
   nir_intrinsic_load_primitive_location_ir3,
   nir_intrinsic_load_printf_buffer_address,
   nir_intrinsic_load_printf_buffer_size,
   nir_intrinsic_load_provoking_last,
   nir_intrinsic_load_provoking_vtx_amd,
   nir_intrinsic_load_provoking_vtx_in_prim_amd,
   nir_intrinsic_load_push_constant,
   nir_intrinsic_load_push_constant_zink,
   nir_intrinsic_load_push_data_intel,
   nir_intrinsic_load_r600_per_vertex_input,
   nir_intrinsic_load_rasterization_primitive_amd,
   nir_intrinsic_load_rasterization_samples_amd,
   nir_intrinsic_load_rasterization_stream,
   nir_intrinsic_load_raw_output_pan,
   nir_intrinsic_load_raw_vertex_id_pan,
   nir_intrinsic_load_raw_vertex_offset_pan,
   nir_intrinsic_load_ray_base_mem_addr_intel,
   nir_intrinsic_load_ray_flags,
   nir_intrinsic_load_ray_geometry_index,
   nir_intrinsic_load_ray_hit_kind,
   nir_intrinsic_load_ray_hit_sbt_addr_intel,
   nir_intrinsic_load_ray_hit_sbt_stride_intel,
   nir_intrinsic_load_ray_hw_stack_size_intel,
   nir_intrinsic_load_ray_instance_custom_index,
   nir_intrinsic_load_ray_launch_id,
   nir_intrinsic_load_ray_launch_size,
   nir_intrinsic_load_ray_miss_sbt_addr_intel,
   nir_intrinsic_load_ray_miss_sbt_stride_intel,
   nir_intrinsic_load_ray_num_dss_rt_stacks_intel,
   nir_intrinsic_load_ray_object_direction,
   nir_intrinsic_load_ray_object_origin,
   nir_intrinsic_load_ray_object_to_world,
   nir_intrinsic_load_ray_payload_ptr_amd,
   nir_intrinsic_load_ray_query_global_intel,
   nir_intrinsic_load_ray_sw_stack_size_intel,
   nir_intrinsic_load_ray_t_max,
   nir_intrinsic_load_ray_t_min,
   nir_intrinsic_load_ray_tracing_stack_base_lvp,
   nir_intrinsic_load_ray_triangle_vertex_positions,
   nir_intrinsic_load_ray_world_direction,
   nir_intrinsic_load_ray_world_origin,
   nir_intrinsic_load_ray_world_to_object,
   nir_intrinsic_load_reg,
   nir_intrinsic_load_reg_indirect,
   nir_intrinsic_load_rel_patch_id_ir3,
   nir_intrinsic_load_reloc_const_intel,
   nir_intrinsic_load_resource_heap_data,
   nir_intrinsic_load_resume_shader_address_amd,
   nir_intrinsic_load_return_param_amd,
   nir_intrinsic_load_ring_attr_amd,
   nir_intrinsic_load_ring_attr_offset_amd,
   nir_intrinsic_load_ring_es2gs_offset_amd,
   nir_intrinsic_load_ring_esgs_amd,
   nir_intrinsic_load_ring_gs2vs_offset_amd,
   nir_intrinsic_load_ring_gsvs_amd,
   nir_intrinsic_load_ring_mesh_scratch_amd,
   nir_intrinsic_load_ring_mesh_scratch_offset_amd,
   nir_intrinsic_load_ring_task_draw_amd,
   nir_intrinsic_load_ring_task_payload_amd,
   nir_intrinsic_load_ring_tess_factors_amd,
   nir_intrinsic_load_ring_tess_factors_offset_amd,
   nir_intrinsic_load_ring_tess_offchip_amd,
   nir_intrinsic_load_ring_tess_offchip_offset_amd,
   nir_intrinsic_load_ro_sink_address_poly,
   nir_intrinsic_load_root_agx,
   nir_intrinsic_load_rt_arg_scratch_offset_amd,
   nir_intrinsic_load_rt_conversion_pan,
   nir_intrinsic_load_rt_descriptors_amd,
   nir_intrinsic_load_rt_dynamic_descriptors_amd,
   nir_intrinsic_load_rt_heap_resource_amd,
   nir_intrinsic_load_rt_heap_sampler_amd,
   nir_intrinsic_load_rt_push_constants_amd,
   nir_intrinsic_load_sample_id,
   nir_intrinsic_load_sample_mask,
   nir_intrinsic_load_sample_mask_in,
   nir_intrinsic_load_sample_pos,
   nir_intrinsic_load_sample_pos_from_id,
   nir_intrinsic_load_sample_pos_or_center,
   nir_intrinsic_load_sample_positions_agx,
   nir_intrinsic_load_sample_positions_amd,
   nir_intrinsic_load_sample_positions_pan,
   nir_intrinsic_load_sampler_handle_agx,
   nir_intrinsic_load_sampler_handle_kk,
   nir_intrinsic_load_sampler_lod_parameters,
   nir_intrinsic_load_samples_log2_agx,
   nir_intrinsic_load_savmsk_vm_pco,
   nir_intrinsic_load_sbt_base_amd,
   nir_intrinsic_load_sbt_offset_amd,
   nir_intrinsic_load_sbt_stride_amd,
   nir_intrinsic_load_scalar_arg_amd,
   nir_intrinsic_load_scratch,
   nir_intrinsic_load_scratch_base_ptr,
   nir_intrinsic_load_scratch_intel,
   nir_intrinsic_load_scratch_nv,
   nir_intrinsic_load_shader_call_data_offset_lvp,
   nir_intrinsic_load_shader_index,
   nir_intrinsic_load_shader_indirect_data_intel,
   nir_intrinsic_load_shader_output_pan,
   nir_intrinsic_load_shader_part_tests_zs_agx,
   nir_intrinsic_load_shader_record_ptr,
   nir_intrinsic_load_shared,
   nir_intrinsic_load_shared2_amd,
   nir_intrinsic_load_shared_base_ptr,
   nir_intrinsic_load_shared_block_intel,
   nir_intrinsic_load_shared_ir3,
   nir_intrinsic_load_shared_lock_nv,
   nir_intrinsic_load_shared_nv,
   nir_intrinsic_load_shared_reg_alloc_size_pco,
   nir_intrinsic_load_shared_uniform_block_intel,
   nir_intrinsic_load_simd_width_intel,
   nir_intrinsic_load_sm_count_nv,
   nir_intrinsic_load_sm_id_nv,
   nir_intrinsic_load_smp_meta_pco,
   nir_intrinsic_load_smp_state_pco,
   nir_intrinsic_load_ssbo,
   nir_intrinsic_load_ssbo_address,
   nir_intrinsic_load_ssbo_block_intel,
   nir_intrinsic_load_ssbo_intel,
   nir_intrinsic_load_ssbo_ir3,
   nir_intrinsic_load_ssbo_uniform_block_intel,
   nir_intrinsic_load_stack,
   nir_intrinsic_load_stat_query_address_poly,
   nir_intrinsic_load_streamout_buffer_amd,
   nir_intrinsic_load_streamout_config_amd,
   nir_intrinsic_load_streamout_offset_amd,
   nir_intrinsic_load_streamout_write_index_amd,
   nir_intrinsic_load_subgroup_eq_mask,
   nir_intrinsic_load_subgroup_ge_mask,
   nir_intrinsic_load_subgroup_gt_mask,
   nir_intrinsic_load_subgroup_id,
   nir_intrinsic_load_subgroup_id_shift_ir3,
   nir_intrinsic_load_subgroup_invocation,
   nir_intrinsic_load_subgroup_le_mask,
   nir_intrinsic_load_subgroup_lt_mask,
   nir_intrinsic_load_subgroup_size,
   nir_intrinsic_load_sysval_agx,
   nir_intrinsic_load_sysval_nv,
   nir_intrinsic_load_task_payload,
   nir_intrinsic_load_task_ring_entry_amd,
   nir_intrinsic_load_tcs_header_ir3,
   nir_intrinsic_load_tcs_in_param_base_r600,
   nir_intrinsic_load_tcs_mem_attrib_stride,
   nir_intrinsic_load_tcs_num_patches_amd,
   nir_intrinsic_load_tcs_out_param_base_r600,
   nir_intrinsic_load_tcs_primitive_mode_amd,
   nir_intrinsic_load_tcs_rel_patch_id_r600,
   nir_intrinsic_load_tcs_tess_factor_base_r600,
   nir_intrinsic_load_tcs_tess_levels_to_tes_amd,
   nir_intrinsic_load_tess_config_intel,
   nir_intrinsic_load_tess_coord,
   nir_intrinsic_load_tess_coord_xy,
   nir_intrinsic_load_tess_factor_base_ir3,
   nir_intrinsic_load_tess_level_inner,
   nir_intrinsic_load_tess_level_inner_default,
   nir_intrinsic_load_tess_level_outer,
   nir_intrinsic_load_tess_level_outer_default,
   nir_intrinsic_load_tess_param_base_ir3,
   nir_intrinsic_load_tess_param_buffer_poly,
   nir_intrinsic_load_tess_rel_patch_id_amd,
   nir_intrinsic_load_tex_meta_pco,
   nir_intrinsic_load_tex_sprite_mask_agx,
   nir_intrinsic_load_tex_state_pco,
   nir_intrinsic_load_texel_buf_conv_pan,
   nir_intrinsic_load_texel_buf_index_address_pan,
   nir_intrinsic_load_texture_handle_agx,
   nir_intrinsic_load_texture_handle_kk,
   nir_intrinsic_load_texture_scale,
   nir_intrinsic_load_texture_size_etna,
   nir_intrinsic_load_tile_coord_pco,
   nir_intrinsic_load_tile_pan,
   nir_intrinsic_load_tile_res_pan,
   nir_intrinsic_load_tiled_offset_pco,
   nir_intrinsic_load_tlb_color_brcm,
   nir_intrinsic_load_topology_id_intel,
   nir_intrinsic_load_ttmp_register_amd,
   nir_intrinsic_load_typed_buffer_amd,
   nir_intrinsic_load_uav_ir3,
   nir_intrinsic_load_ubo,
   nir_intrinsic_load_ubo_uniform_block_intel,
   nir_intrinsic_load_ubo_vec4,
   nir_intrinsic_load_uniform,
   nir_intrinsic_load_urb_input_handle_indexed_intel,
   nir_intrinsic_load_urb_input_handle_intel,
   nir_intrinsic_load_urb_lsc_intel,
   nir_intrinsic_load_urb_output_handle_intel,
   nir_intrinsic_load_urb_vec4_intel,
   nir_intrinsic_load_user_clip_plane,
   nir_intrinsic_load_user_data_amd,
   nir_intrinsic_load_uvs_index_agx,
   nir_intrinsic_load_var_buf_flat_pan,
   nir_intrinsic_load_var_buf_pan,
   nir_intrinsic_load_var_flat_pan,
   nir_intrinsic_load_var_pan,
   nir_intrinsic_load_var_special_pan,
   nir_intrinsic_load_vbo_base_agx,
   nir_intrinsic_load_vbo_stride_agx,
   nir_intrinsic_load_vector_arg_amd,
   nir_intrinsic_load_vertex_id,
   nir_intrinsic_load_vertex_id_zero_base,
   nir_intrinsic_load_vertex_param_buffer_poly,
   nir_intrinsic_load_view_index,
   nir_intrinsic_load_viewport_offset,
   nir_intrinsic_load_viewport_scale,
   nir_intrinsic_load_viewport_x_offset,
   nir_intrinsic_load_viewport_x_scale,
   nir_intrinsic_load_viewport_y_offset,
   nir_intrinsic_load_viewport_y_scale,
   nir_intrinsic_load_viewport_z_offset,
   nir_intrinsic_load_viewport_z_scale,
   nir_intrinsic_load_vs_outputs_poly,
   nir_intrinsic_load_vs_primitive_stride_ir3,
   nir_intrinsic_load_vs_vertex_stride_ir3,
   nir_intrinsic_load_vtxin_pco,
   nir_intrinsic_load_vulkan_descriptor,
   nir_intrinsic_load_warp_id_arm,
   nir_intrinsic_load_warp_id_nv,
   nir_intrinsic_load_warp_max_id_arm,
   nir_intrinsic_load_warps_per_sm_nv,
   nir_intrinsic_load_work_dim,
   nir_intrinsic_load_workgroup_id,
   nir_intrinsic_load_workgroup_index,
   nir_intrinsic_load_workgroup_num_input_primitives_amd,
   nir_intrinsic_load_workgroup_num_input_vertices_amd,
   nir_intrinsic_load_workgroup_size,
   nir_intrinsic_load_xfb_address,
   nir_intrinsic_load_xfb_index_buffer,
   nir_intrinsic_load_xfb_size,
   nir_intrinsic_load_xfb_state_address_gfx12_amd,
   nir_intrinsic_masked_swizzle_amd,
   nir_intrinsic_mbcnt_amd,
   nir_intrinsic_memcpy_deref,
   nir_intrinsic_mutex_pco,
   nir_intrinsic_nop,
   nir_intrinsic_nop_amd,
   nir_intrinsic_optimization_barrier_sgpr_amd,
   nir_intrinsic_optimization_barrier_vgpr_amd,
   nir_intrinsic_ordered_add_loop_gfx12_amd,
   nir_intrinsic_ordered_xfb_counter_add_gfx11_amd,
   nir_intrinsic_overwrite_tes_arguments_amd,
   nir_intrinsic_overwrite_vs_arguments_amd,
   nir_intrinsic_pack_pco,
   nir_intrinsic_parallel_copy,
   nir_intrinsic_pck_prog_pco,
   nir_intrinsic_pin_cx_handle_nv,
   nir_intrinsic_preamble_end_ir3,
   nir_intrinsic_preamble_start_ir3,
   nir_intrinsic_prefetch_sam_ir3,
   nir_intrinsic_prefetch_tex_ir3,
   nir_intrinsic_prefetch_ubo_ir3,
   nir_intrinsic_printf,
   nir_intrinsic_printf_abort,
   nir_intrinsic_quad_ballot_agx,
   nir_intrinsic_quad_broadcast,
   nir_intrinsic_quad_swap_diagonal,
   nir_intrinsic_quad_swap_horizontal,
   nir_intrinsic_quad_swap_vertical,
   nir_intrinsic_quad_swizzle_amd,
   nir_intrinsic_quad_vote_all,
   nir_intrinsic_quad_vote_any,
   nir_intrinsic_r600_indirect_vertex_at_index,
   nir_intrinsic_ray_intersection_ir3,
   nir_intrinsic_read_first_invocation,
   nir_intrinsic_read_getlast_ir3,
   nir_intrinsic_read_invocation,
   nir_intrinsic_read_invocation_cond_ir3,
   nir_intrinsic_reduce,
   nir_intrinsic_reduce_clusters_ir3,
   nir_intrinsic_report_ray_intersection,
   nir_intrinsic_resource_intel,
   nir_intrinsic_ro_to_rw_poly,
   nir_intrinsic_rotate,
   nir_intrinsic_rq_confirm_intersection,
   nir_intrinsic_rq_generate_intersection,
   nir_intrinsic_rq_initialize,
   nir_intrinsic_rq_load,
   nir_intrinsic_rq_proceed,
   nir_intrinsic_rq_terminate,
   nir_intrinsic_rt_execute_callable,
   nir_intrinsic_rt_resume,
   nir_intrinsic_rt_return_amd,
   nir_intrinsic_rt_trace_ray,
   nir_intrinsic_sample_mask_agx,
   nir_intrinsic_select_vertex_poly,
   nir_intrinsic_sendmsg_amd,
   nir_intrinsic_set_next_call_pc_amd,
   nir_intrinsic_set_vertex_and_primitive_count,
   nir_intrinsic_shader_clock,
   nir_intrinsic_shared_append_amd,
   nir_intrinsic_shared_atomic,
   nir_intrinsic_shared_atomic_nv,
   nir_intrinsic_shared_atomic_swap,
   nir_intrinsic_shared_atomic_swap_nv,
   nir_intrinsic_shared_consume_amd,
   nir_intrinsic_shuffle,
   nir_intrinsic_shuffle_down,
   nir_intrinsic_shuffle_down_intel,
   nir_intrinsic_shuffle_down_uniform_ir3,
   nir_intrinsic_shuffle_intel,
   nir_intrinsic_shuffle_up,
   nir_intrinsic_shuffle_up_intel,
   nir_intrinsic_shuffle_up_uniform_ir3,
   nir_intrinsic_shuffle_xor,
   nir_intrinsic_shuffle_xor_uniform_ir3,
   nir_intrinsic_sleep_amd,
   nir_intrinsic_smp_coeffs_pco,
   nir_intrinsic_smp_pco,
   nir_intrinsic_smp_raw_pco,
   nir_intrinsic_smp_write_pco,
   nir_intrinsic_sparse_residency_code_and,
   nir_intrinsic_ssa_bar_nv,
   nir_intrinsic_ssbo_atomic,
   nir_intrinsic_ssbo_atomic_ir3,
   nir_intrinsic_ssbo_atomic_swap,
   nir_intrinsic_ssbo_atomic_swap_ir3,
   nir_intrinsic_ssbo_descriptor_amd,
   nir_intrinsic_stack_map_agx,
   nir_intrinsic_stack_unmap_agx,
   nir_intrinsic_store_agx,
   nir_intrinsic_store_buffer_amd,
   nir_intrinsic_store_clip_distance_kk,
   nir_intrinsic_store_combined_output_pan,
   nir_intrinsic_store_const_ir3,
   nir_intrinsic_store_deref,
   nir_intrinsic_store_deref_block_intel,
   nir_intrinsic_store_global,
   nir_intrinsic_store_global_2x32,
   nir_intrinsic_store_global_amd,
   nir_intrinsic_store_global_block_intel,
   nir_intrinsic_store_global_cvt_pan,
   nir_intrinsic_store_global_etna,
   nir_intrinsic_store_global_ir3,
   nir_intrinsic_store_global_nv,
   nir_intrinsic_store_global_psiz_pan,
   nir_intrinsic_store_hit_attrib_amd,
   nir_intrinsic_store_incoming_ray_payload_amd,
   nir_intrinsic_store_local_pixel_agx,
   nir_intrinsic_store_local_shared_r600,
   nir_intrinsic_store_outgoing_ray_payload_amd,
   nir_intrinsic_store_output,
   nir_intrinsic_store_param_amd,
   nir_intrinsic_store_per_primitive_output,
   nir_intrinsic_store_per_primitive_payload_intel,
   nir_intrinsic_store_per_vertex_output,
   nir_intrinsic_store_per_view_output,
   nir_intrinsic_store_pixel_local,
   nir_intrinsic_store_preamble,
   nir_intrinsic_store_preamble_dynamic,
   nir_intrinsic_store_raw_output_pan,
   nir_intrinsic_store_reg,
   nir_intrinsic_store_reg_indirect,
   nir_intrinsic_store_render_target_intel,
   nir_intrinsic_store_scalar_arg_amd,
   nir_intrinsic_store_scratch,
   nir_intrinsic_store_scratch_intel,
   nir_intrinsic_store_scratch_nv,
   nir_intrinsic_store_shared,
   nir_intrinsic_store_shared2_amd,
   nir_intrinsic_store_shared_block_intel,
   nir_intrinsic_store_shared_ir3,
   nir_intrinsic_store_shared_nv,
   nir_intrinsic_store_shared_unlock_nv,
   nir_intrinsic_store_ssbo,
   nir_intrinsic_store_ssbo_block_intel,
   nir_intrinsic_store_ssbo_intel,
   nir_intrinsic_store_ssbo_ir3,
   nir_intrinsic_store_stack,
   nir_intrinsic_store_task_payload,
   nir_intrinsic_store_tf_r600,
   nir_intrinsic_store_tile_pan,
   nir_intrinsic_store_tlb_sample_color_v3d,
   nir_intrinsic_store_urb_lsc_intel,
   nir_intrinsic_store_urb_vec4_intel,
   nir_intrinsic_store_uvs_agx,
   nir_intrinsic_store_vector_arg_amd,
   nir_intrinsic_store_zs_agx,
   nir_intrinsic_strict_wqm_coord_amd,
   nir_intrinsic_subfm_nv,
   nir_intrinsic_suclamp_nv,
   nir_intrinsic_sueau_nv,
   nir_intrinsic_suldga_nv,
   nir_intrinsic_sustga_nv,
   nir_intrinsic_task_payload_atomic,
   nir_intrinsic_task_payload_atomic_swap,
   nir_intrinsic_terminate,
   nir_intrinsic_terminate_if,
   nir_intrinsic_terminate_ray,
   nir_intrinsic_trace_ray,
   nir_intrinsic_trace_ray_intel,
   nir_intrinsic_unit_test_assert_eq,
   nir_intrinsic_unit_test_divergent_input,
   nir_intrinsic_unit_test_output,
   nir_intrinsic_unit_test_uniform_input,
   nir_intrinsic_unpack_pco,
   nir_intrinsic_unpin_cx_handle_nv,
   nir_intrinsic_use,
   nir_intrinsic_uvsw_write_pco,
   nir_intrinsic_vild_nv,
   nir_intrinsic_vote_all,
   nir_intrinsic_vote_any,
   nir_intrinsic_vote_feq,
   nir_intrinsic_vote_ieq,
   nir_intrinsic_vulkan_resource_index,
   nir_intrinsic_vulkan_resource_reindex,
   nir_intrinsic_wop_pco,
   nir_intrinsic_write_invocation_amd,
   nir_intrinsic_xfb_counter_sub_gfx11_amd,
   nir_intrinsic_zs_emit_pan,

   nir_last_intrinsic = nir_intrinsic_zs_emit_pan,
   nir_num_intrinsics = nir_last_intrinsic + 1
} nir_intrinsic_op;

typedef enum {
   NIR_INTRINSIC_BASE,
   NIR_INTRINSIC_WRITE_MASK,
   NIR_INTRINSIC_ENABLED_CHANNELS,
   NIR_INTRINSIC_TARGET,
   NIR_INTRINSIC_STREAM_ID,
   NIR_INTRINSIC_UCP_ID,
   NIR_INTRINSIC_RANGE_BASE,
   NIR_INTRINSIC_RANGE,
   NIR_INTRINSIC_DESC_SET,
   NIR_INTRINSIC_BINDING,
   NIR_INTRINSIC_COMPONENT,
   NIR_INTRINSIC_COLUMN,
   NIR_INTRINSIC_INTERP_MODE,
   NIR_INTRINSIC_REDUCTION_OP,
   NIR_INTRINSIC_CLUSTER_SIZE,
   NIR_INTRINSIC_PARAM_IDX,
   NIR_INTRINSIC_IMAGE_DIM,
   NIR_INTRINSIC_IMAGE_ARRAY,
   NIR_INTRINSIC_FORMAT,
   NIR_INTRINSIC_ACCESS,
   NIR_INTRINSIC_CALL_IDX,
   NIR_INTRINSIC_STACK_SIZE,
   NIR_INTRINSIC_ALIGN_MUL,
   NIR_INTRINSIC_ALIGN_OFFSET,
   NIR_INTRINSIC_OFFSET_SHIFT,
   NIR_INTRINSIC_OFFSET_SHIFT_NV,
   NIR_INTRINSIC_DESC_TYPE,
   NIR_INTRINSIC_RESOURCE_TYPE,
   NIR_INTRINSIC_SRC_TYPE,
   NIR_INTRINSIC_DEST_TYPE,
   NIR_INTRINSIC_SRC_BASE_TYPE,
   NIR_INTRINSIC_SRC_BASE_TYPE2,
   NIR_INTRINSIC_DEST_BASE_TYPE,
   NIR_INTRINSIC_SWIZZLE_MASK,
   NIR_INTRINSIC_FETCH_INACTIVE,
   NIR_INTRINSIC_OFFSET0,
   NIR_INTRINSIC_OFFSET1,
   NIR_INTRINSIC_ST64,
   NIR_INTRINSIC_ARG_UPPER_BOUND_U32_AMD,
   NIR_INTRINSIC_DST_ACCESS,
   NIR_INTRINSIC_SRC_ACCESS,
   NIR_INTRINSIC_DRIVER_LOCATION,
   NIR_INTRINSIC_MEMORY_SEMANTICS,
   NIR_INTRINSIC_MEMORY_MODES,
   NIR_INTRINSIC_MEMORY_SCOPE,
   NIR_INTRINSIC_EXECUTION_SCOPE,
   NIR_INTRINSIC_IO_SEMANTICS,
   NIR_INTRINSIC_IO_XFB,
   NIR_INTRINSIC_RAY_QUERY_VALUE,
   NIR_INTRINSIC_COMMITTED,
   NIR_INTRINSIC_ROUNDING_MODE,
   NIR_INTRINSIC_SATURATE,
   NIR_INTRINSIC_SYNCHRONOUS,
   NIR_INTRINSIC_VALUE_ID,
   NIR_INTRINSIC_SIGN_EXTEND,
   NIR_INTRINSIC_FLAGS,
   NIR_INTRINSIC_ATOMIC_OP,
   NIR_INTRINSIC_RESOURCE_BLOCK_INTEL,
   NIR_INTRINSIC_RESOURCE_ACCESS_INTEL,
   NIR_INTRINSIC_NUM_COMPONENTS,
   NIR_INTRINSIC_NUM_ARRAY_ELEMS,
   NIR_INTRINSIC_BIT_SIZE,
   NIR_INTRINSIC_DIVERGENT,
   NIR_INTRINSIC_LEGACY_FABS,
   NIR_INTRINSIC_LEGACY_FNEG,
   NIR_INTRINSIC_LEGACY_FSAT,
   NIR_INTRINSIC_CMAT_DESC,
   NIR_INTRINSIC_MATRIX_LAYOUT,
   NIR_INTRINSIC_CMAT_SIGNED_MASK,
   NIR_INTRINSIC_ALU_OP,
   NIR_INTRINSIC_NEG_LO_AMD,
   NIR_INTRINSIC_NEG_HI_AMD,
   NIR_INTRINSIC_SYSTOLIC_DEPTH,
   NIR_INTRINSIC_REPEAT_COUNT,
   NIR_INTRINSIC_DST_CMAT_DESC,
   NIR_INTRINSIC_SRC_CMAT_DESC,
   NIR_INTRINSIC_EXPLICIT_COORD,
   NIR_INTRINSIC_SRC_IS_REG,
   NIR_INTRINSIC_DST_IS_REG,
   NIR_INTRINSIC_EOT,
   NIR_INTRINSIC_FMT_IDX,
   NIR_INTRINSIC_NUM_MATRICES,
   NIR_INTRINSIC_PREAMBLE_CLASS,
   NIR_INTRINSIC_FP_MATH_CTRL,
   NIR_INTRINSIC_SMP_FLAGS_PCO,
   NIR_INTRINSIC_MUTEX_ID_PCO,
   NIR_INTRINSIC_MUTEX_OP_PCO,
   NIR_INTRINSIC_FREEP,
   NIR_INTRINSIC_SCALE,
   NIR_INTRINSIC_ROUNDZERO,
   NIR_INTRINSIC_NUM_INDEX_FLAGS,
} nir_intrinsic_index_flag;

extern const char *nir_intrinsic_index_names[NIR_INTRINSIC_NUM_INDEX_FLAGS];

#endif /* _NIR_INTRINSICS_ */
