Electronic Lab

perl-Verilog-Readmem - Parse Verilog $readmemh or $readmemb text file

Website: http://search.cpan.org/dist/Verilog-Readmem/
License: GPL+ or Artistic
Description:
The Verilog Hardware Description Language (HDL) provides a convenient way
to load a memory during logic simulation. The $readmemh() and $readmemb()
system tasks are used in the HDL source code to import the contents of a
text file into a memory variable.

Packages

perl-Verilog-Readmem-0.04-2m.mo6.noarch [13 KiB] Changelog by NAKAYA Toshiharu (2009-07-01):
- (0.04-2m)
- remove duplicate directories

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