<html><head><meta name="color-scheme" content="light dark"></head><body><pre style="word-wrap: break-word; white-space: pre-wrap;">! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh but no more.
! If the tests are failing because the expected results have changed then run
!    'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in &lt;srcdir&gt;/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.

	.section .text
sh:
! Instructions introduced into sh
	add #4,r4                 ;!/* 0111nnnni8*1.... add #&lt;imm&gt;,&lt;REG_N&gt;  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
	add r5,r4                 ;!/* 0011nnnnmmmm1100 add &lt;REG_M&gt;,&lt;REG_N&gt; */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc &lt;REG_M&gt;,&lt;REG_N&gt;*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv &lt;REG_M&gt;,&lt;REG_N&gt;*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
	and #4,R0                 ;!/* 11001001i8*1.... and #&lt;imm&gt;,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
	and r5,r4                 ;!/* 0010nnnnmmmm1001 and &lt;REG_M&gt;,&lt;REG_N&gt; */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #&lt;imm&gt;,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
	bra .+8                   ;!/* 1010i12......... bra &lt;bdisp12&gt;       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
	bsr .+8                   ;!/* 1011i12......... bsr &lt;bdisp12&gt;       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
	bt .+8                    ;!/* 10001001i8p1.... bt &lt;bdisp8&gt;         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
	bf .+8                    ;!/* 10001011i8p1.... bf &lt;bdisp8&gt;         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #&lt;imm&gt;,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq &lt;REG_M&gt;,&lt;REG_N&gt;*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge &lt;REG_M&gt;,&lt;REG_N&gt;*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt &lt;REG_M&gt;,&lt;REG_N&gt;*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi &lt;REG_M&gt;,&lt;REG_N&gt;*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs &lt;REG_M&gt;,&lt;REG_N&gt;*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl &lt;REG_N&gt;      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz &lt;REG_N&gt;      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str &lt;REG_M&gt;,&lt;REG_N&gt;*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s &lt;REG_M&gt;,&lt;REG_N&gt;*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 &lt;REG_M&gt;,&lt;REG_N&gt;*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b &lt;REG_M&gt;,&lt;REG_N&gt;*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w &lt;REG_M&gt;,&lt;REG_N&gt;*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b &lt;REG_M&gt;,&lt;REG_N&gt;*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w &lt;REG_M&gt;,&lt;REG_N&gt;*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
	jmp @r4                   ;!/* 0100nnnn00101011 jmp @&lt;REG_N&gt;        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
	jsr @r4                   ;!/* 0100nnnn00001011 jsr @&lt;REG_N&gt;        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc &lt;REG_N&gt;,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc &lt;REG_N&gt;,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc &lt;REG_N&gt;,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @&lt;REG_N&gt;+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @&lt;REG_N&gt;+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @&lt;REG_N&gt;+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
	lds r4,MACH               ;!/* 0100nnnn00001010 lds &lt;REG_N&gt;,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
	lds r4,MACL               ;!/* 0100nnnn00011010 lds &lt;REG_N&gt;,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
	lds r4,PR                 ;!/* 0100nnnn00101010 lds &lt;REG_N&gt;,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @&lt;REG_N&gt;+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @&lt;REG_N&gt;+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @&lt;REG_N&gt;+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @&lt;REG_M&gt;+,@&lt;REG_N&gt;+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #&lt;imm&gt;,&lt;REG_N&gt;  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov &lt;REG_M&gt;,&lt;REG_N&gt; */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b &lt;REG_M&gt;,@(R0,&lt;REG_N&gt;)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b &lt;REG_M&gt;,@-&lt;REG_N&gt;*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b &lt;REG_M&gt;,@&lt;REG_N&gt;*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(&lt;disp&gt;,&lt;REG_M&gt;),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(&lt;disp&gt;,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,&lt;REG_M&gt;),&lt;REG_N&gt;*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @&lt;REG_M&gt;+,&lt;REG_N&gt;*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @&lt;REG_M&gt;,&lt;REG_N&gt;*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(&lt;disp&gt;,&lt;REG_M&gt;)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(&lt;disp&gt;,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l &lt;REG_M&gt;,@(&lt;disp&gt;,&lt;REG_N&gt;)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l &lt;REG_M&gt;,@(R0,&lt;REG_N&gt;)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l &lt;REG_M&gt;,@-&lt;REG_N&gt;*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l &lt;REG_M&gt;,@&lt;REG_N&gt;*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(&lt;disp&gt;,&lt;REG_M&gt;),&lt;REG_N&gt;*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(&lt;disp&gt;,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
	.align 2
	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(&lt;disp&gt;,PC),&lt;REG_N&gt;*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,&lt;REG_M&gt;),&lt;REG_N&gt;*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @&lt;REG_M&gt;+,&lt;REG_N&gt;*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @&lt;REG_M&gt;,&lt;REG_N&gt;*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(&lt;disp&gt;,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w &lt;REG_M&gt;,@(R0,&lt;REG_N&gt;)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w &lt;REG_M&gt;,@-&lt;REG_N&gt;*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w &lt;REG_M&gt;,@&lt;REG_N&gt;*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(&lt;disp&gt;,&lt;REG_M&gt;),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(&lt;disp&gt;,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(&lt;disp&gt;,PC),&lt;REG_N&gt;*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,&lt;REG_M&gt;),&lt;REG_N&gt;*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @&lt;REG_M&gt;+,&lt;REG_N&gt;*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @&lt;REG_M&gt;,&lt;REG_N&gt;*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(&lt;disp&gt;,&lt;REG_M&gt;)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(&lt;disp&gt;,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
	.align 2
	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(&lt;disp&gt;,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
	movt r4                   ;!/* 0000nnnn00101001 movt &lt;REG_N&gt;        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w &lt;REG_M&gt;,&lt;REG_N&gt;*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls &lt;REG_M&gt;,&lt;REG_N&gt;*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w &lt;REG_M&gt;,&lt;REG_N&gt;*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu &lt;REG_M&gt;,&lt;REG_N&gt;*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg &lt;REG_M&gt;,&lt;REG_N&gt; */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc &lt;REG_M&gt;,&lt;REG_N&gt;*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
	not r5,r4                 ;!/* 0110nnnnmmmm0111 not &lt;REG_M&gt;,&lt;REG_N&gt; */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
	or #4,R0                  ;!/* 11001011i8*1.... or #&lt;imm&gt;,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
	or r5,r4                  ;!/* 0010nnnnmmmm1011 or &lt;REG_M&gt;,&lt;REG_N&gt;  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #&lt;imm&gt;,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
	rotcl r4                  ;!/* 0100nnnn00100100 rotcl &lt;REG_N&gt;       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
	rotcr r4                  ;!/* 0100nnnn00100101 rotcr &lt;REG_N&gt;       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
	rotl r4                   ;!/* 0100nnnn00000100 rotl &lt;REG_N&gt;        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
	rotr r4                   ;!/* 0100nnnn00000101 rotr &lt;REG_N&gt;        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
	shal r4                   ;!/* 0100nnnn00100000 shal &lt;REG_N&gt;        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
	shar r4                   ;!/* 0100nnnn00100001 shar &lt;REG_N&gt;        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
	shll r4                   ;!/* 0100nnnn00000000 shll &lt;REG_N&gt;        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
	shll16 r4                 ;!/* 0100nnnn00101000 shll16 &lt;REG_N&gt;      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
	shll2 r4                  ;!/* 0100nnnn00001000 shll2 &lt;REG_N&gt;       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
	shll8 r4                  ;!/* 0100nnnn00011000 shll8 &lt;REG_N&gt;       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
	shlr r4                   ;!/* 0100nnnn00000001 shlr &lt;REG_N&gt;        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 &lt;REG_N&gt;      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 &lt;REG_N&gt;       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 &lt;REG_N&gt;       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,&lt;REG_N&gt;      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,&lt;REG_N&gt;     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,&lt;REG_N&gt;     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-&lt;REG_N&gt;  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-&lt;REG_N&gt; */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-&lt;REG_N&gt; */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,&lt;REG_N&gt;    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,&lt;REG_N&gt;    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,&lt;REG_N&gt;      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-&lt;REG_N&gt;*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-&lt;REG_N&gt;*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-&lt;REG_N&gt;  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub &lt;REG_M&gt;,&lt;REG_N&gt; */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc &lt;REG_M&gt;,&lt;REG_N&gt;*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv &lt;REG_M&gt;,&lt;REG_N&gt;*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b &lt;REG_M&gt;,&lt;REG_N&gt;*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w &lt;REG_M&gt;,&lt;REG_N&gt;*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @&lt;REG_N&gt;      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
	trapa #4                  ;!/* 11000011i8*1.... trapa #&lt;imm&gt;        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
	tst #4,R0                 ;!/* 11001000i8*1.... tst #&lt;imm&gt;,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst &lt;REG_M&gt;,&lt;REG_N&gt; */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #&lt;imm&gt;,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
	xor #4,R0                 ;!/* 11001010i8*1.... xor #&lt;imm&gt;,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor &lt;REG_M&gt;,&lt;REG_N&gt; */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #&lt;imm&gt;,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct &lt;REG_M&gt;,&lt;REG_N&gt;*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}

! Instructions inherited from ancestors:
</pre></body></html>