<html><head><meta name="color-scheme" content="light dark"></head><body><pre style="word-wrap: break-word; white-space: pre-wrap;">! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh3-dsp but no more.
! If the tests are failing because the expected results have changed then run
!    'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in &lt;srcdir&gt;/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.

	.section .text
sh3_dsp:
! Instructions introduced into sh3-dsp

! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
	add #4,r4                 ;!/* 0111nnnni8*1.... add #&lt;imm&gt;,&lt;REG_N&gt;  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
	add r5,r4                 ;!/* 0011nnnnmmmm1100 add &lt;REG_M&gt;,&lt;REG_N&gt; */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc &lt;REG_M&gt;,&lt;REG_N&gt;*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv &lt;REG_M&gt;,&lt;REG_N&gt;*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
	and #4,R0                 ;!/* 11001001i8*1.... and #&lt;imm&gt;,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
	and r5,r4                 ;!/* 0010nnnnmmmm1001 and &lt;REG_M&gt;,&lt;REG_N&gt; */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #&lt;imm&gt;,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
	bra .+8                   ;!/* 1010i12......... bra &lt;bdisp12&gt;       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
	bsr .+8                   ;!/* 1011i12......... bsr &lt;bdisp12&gt;       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
	bt .+8                    ;!/* 10001001i8p1.... bt &lt;bdisp8&gt;         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
	bf .+8                    ;!/* 10001011i8p1.... bf &lt;bdisp8&gt;         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
	bt.s .+8                  ;!/* 10001101i8p1.... bt.s &lt;bdisp8&gt;       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
	bt/s .+8                  ;!/* 10001101i8p1.... bt/s &lt;bdisp8&gt;       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
	bf.s .+8                  ;!/* 10001111i8p1.... bf.s &lt;bdisp8&gt;       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
	bf/s .+8                  ;!/* 10001111i8p1.... bf/s &lt;bdisp8&gt;       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up}
	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #&lt;imm&gt;,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq &lt;REG_M&gt;,&lt;REG_N&gt;*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge &lt;REG_M&gt;,&lt;REG_N&gt;*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt &lt;REG_M&gt;,&lt;REG_N&gt;*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi &lt;REG_M&gt;,&lt;REG_N&gt;*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs &lt;REG_M&gt;,&lt;REG_N&gt;*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl &lt;REG_N&gt;      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz &lt;REG_N&gt;      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str &lt;REG_M&gt;,&lt;REG_N&gt;*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s &lt;REG_M&gt;,&lt;REG_N&gt;*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 &lt;REG_M&gt;,&lt;REG_N&gt;*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b &lt;REG_M&gt;,&lt;REG_N&gt;*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w &lt;REG_M&gt;,&lt;REG_N&gt;*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b &lt;REG_M&gt;,&lt;REG_N&gt;*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w &lt;REG_M&gt;,&lt;REG_N&gt;*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
	jmp @r4                   ;!/* 0100nnnn00101011 jmp @&lt;REG_N&gt;        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
	jsr @r4                   ;!/* 0100nnnn00001011 jsr @&lt;REG_N&gt;        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc &lt;REG_N&gt;,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc &lt;REG_N&gt;,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc &lt;REG_N&gt;,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
	ldc r4,MOD                ;!/* 0100nnnn01011110 ldc &lt;REG_N&gt;,MOD     */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}
	ldc r4,RE                 ;!/* 0100nnnn01111110 ldc &lt;REG_N&gt;,RE     */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}
	ldc r4,RS                 ;!/* 0100nnnn01101110 ldc &lt;REG_N&gt;,RS     */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}
	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc &lt;REG_N&gt;,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc &lt;REG_N&gt;,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc &lt;REG_N&gt;,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @&lt;REG_N&gt;+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @&lt;REG_N&gt;+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @&lt;REG_N&gt;+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
	ldc.l @r4+,MOD            ;!/* 0100nnnn01010111 ldc.l @&lt;REG_N&gt;+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}
	ldc.l @r4+,RE             ;!/* 0100nnnn01110111 ldc.l @&lt;REG_N&gt;+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}
	ldc.l @r4+,RS             ;!/* 0100nnnn01100111 ldc.l @&lt;REG_N&gt;+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up}
	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @&lt;REG_N&gt;+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @&lt;REG_N&gt;+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @&lt;REG_N&gt;+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
	ldre @(8,PC)              ;!/* 10001110i8p2.... ldre @(&lt;disp&gt;,PC)	*/{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up}
	ldrs @(8,PC)              ;!/* 10001100i8p2.... ldrs @(&lt;disp&gt;,PC)	*/{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up}
	lds r4,MACH               ;!/* 0100nnnn00001010 lds &lt;REG_N&gt;,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
	lds r4,MACL               ;!/* 0100nnnn00011010 lds &lt;REG_N&gt;,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
	lds r4,PR                 ;!/* 0100nnnn00101010 lds &lt;REG_N&gt;,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
	lds r4,DSR                ;!/* 0100nnnn01101010 lds &lt;REG_N&gt;,DSR	*/{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
	lds r4,A0                 ;!/* 0100nnnn01111010 lds &lt;REG_N&gt;,A0	*/{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
	lds r4,X0                 ;!/* 0100nnnn10001010 lds &lt;REG_N&gt;,X0	*/{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
	lds r4,X1                 ;!/* 0100nnnn10011010 lds &lt;REG_N&gt;,X1	*/{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
	lds r4,Y0                 ;!/* 0100nnnn10101010 lds &lt;REG_N&gt;,Y0	*/{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
	lds r4,Y1                 ;!/* 0100nnnn10111010 lds &lt;REG_N&gt;,Y1	*/{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @&lt;REG_N&gt;+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @&lt;REG_N&gt;+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @&lt;REG_N&gt;+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
	lds.l @r4+,DSR            ;!/* 0100nnnn01100110 lds.l @&lt;REG_N&gt;+,DSR	*/{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up}
	lds.l @r4+,A0             ;!/* 0100nnnn01110110 lds.l @&lt;REG_N&gt;+,A0	*/{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up}
	lds.l @r4+,X0             ;!/* 0100nnnn10000110 lds.l @&lt;REG_N&gt;+,X0	*/{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up}
	lds.l @r4+,X1             ;!/* 0100nnnn10010110 lds.l @&lt;REG_N&gt;+,X1	*/{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up}
	lds.l @r4+,Y0             ;!/* 0100nnnn10100110 lds.l @&lt;REG_N&gt;+,Y0	*/{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up}
	lds.l @r4+,Y1             ;!/* 0100nnnn10110110 lds.l @&lt;REG_N&gt;+,Y1	*/{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}
	ldtlb                     ;!/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @&lt;REG_M&gt;+,@&lt;REG_N&gt;+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #&lt;imm&gt;,&lt;REG_N&gt;  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov &lt;REG_M&gt;,&lt;REG_N&gt; */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b &lt;REG_M&gt;,@(R0,&lt;REG_N&gt;)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b &lt;REG_M&gt;,@-&lt;REG_N&gt;*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b &lt;REG_M&gt;,@&lt;REG_N&gt;*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(&lt;disp&gt;,&lt;REG_M&gt;),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(&lt;disp&gt;,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,&lt;REG_M&gt;),&lt;REG_N&gt;*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @&lt;REG_M&gt;+,&lt;REG_N&gt;*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @&lt;REG_M&gt;,&lt;REG_N&gt;*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(&lt;disp&gt;,&lt;REG_M&gt;)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(&lt;disp&gt;,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l &lt;REG_M&gt;,@(&lt;disp&gt;,&lt;REG_N&gt;)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l &lt;REG_M&gt;,@(R0,&lt;REG_N&gt;)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l &lt;REG_M&gt;,@-&lt;REG_N&gt;*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l &lt;REG_M&gt;,@&lt;REG_N&gt;*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(&lt;disp&gt;,&lt;REG_M&gt;),&lt;REG_N&gt;*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(&lt;disp&gt;,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
	.align 2
	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(&lt;disp&gt;,PC),&lt;REG_N&gt;*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,&lt;REG_M&gt;),&lt;REG_N&gt;*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @&lt;REG_M&gt;+,&lt;REG_N&gt;*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @&lt;REG_M&gt;,&lt;REG_N&gt;*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(&lt;disp&gt;,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w &lt;REG_M&gt;,@(R0,&lt;REG_N&gt;)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w &lt;REG_M&gt;,@-&lt;REG_N&gt;*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w &lt;REG_M&gt;,@&lt;REG_N&gt;*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(&lt;disp&gt;,&lt;REG_M&gt;),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(&lt;disp&gt;,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(&lt;disp&gt;,PC),&lt;REG_N&gt;*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,&lt;REG_M&gt;),&lt;REG_N&gt;*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @&lt;REG_M&gt;+,&lt;REG_N&gt;*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @&lt;REG_M&gt;,&lt;REG_N&gt;*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(&lt;disp&gt;,&lt;REG_M&gt;)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(&lt;disp&gt;,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
	.align 2
	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(&lt;disp&gt;,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
	movt r4                   ;!/* 0000nnnn00101001 movt &lt;REG_N&gt;        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w &lt;REG_M&gt;,&lt;REG_N&gt;*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls &lt;REG_M&gt;,&lt;REG_N&gt;*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l &lt;REG_M&gt;,&lt;REG_N&gt;*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w &lt;REG_M&gt;,&lt;REG_N&gt;*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu &lt;REG_M&gt;,&lt;REG_N&gt;*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg &lt;REG_M&gt;,&lt;REG_N&gt; */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc &lt;REG_M&gt;,&lt;REG_N&gt;*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
	not r5,r4                 ;!/* 0110nnnnmmmm0111 not &lt;REG_M&gt;,&lt;REG_N&gt; */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
	or #4,R0                  ;!/* 11001011i8*1.... or #&lt;imm&gt;,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
	or r5,r4                  ;!/* 0010nnnnmmmm1011 or &lt;REG_M&gt;,&lt;REG_N&gt;  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #&lt;imm&gt;,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
	pref @r4                  ;!/* 0000nnnn10000011 pref @&lt;REG_N&gt;       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
	rotcl r4                  ;!/* 0100nnnn00100100 rotcl &lt;REG_N&gt;       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
	rotcr r4                  ;!/* 0100nnnn00100101 rotcr &lt;REG_N&gt;       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
	rotl r4                   ;!/* 0100nnnn00000100 rotl &lt;REG_N&gt;        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
	rotr r4                   ;!/* 0100nnnn00000101 rotr &lt;REG_N&gt;        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
	setrc r4                  ;!/* 0100nnnn00010100 setrc &lt;REG_N&gt;       */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
	setrc #4                  ;!/* 10000010i8*1.... setrc #&lt;imm&gt;        */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
	repeat 10 20 r4           ;!/* repeat start end &lt;REG_N&gt;       	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
	repeat 10 20 #4           ;!/* repeat start end #&lt;imm&gt;        	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad &lt;REG_M&gt;,&lt;REG_N&gt;*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld &lt;REG_M&gt;,&lt;REG_N&gt;*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
	shal r4                   ;!/* 0100nnnn00100000 shal &lt;REG_N&gt;        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
	shar r4                   ;!/* 0100nnnn00100001 shar &lt;REG_N&gt;        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
	shll r4                   ;!/* 0100nnnn00000000 shll &lt;REG_N&gt;        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
	shll16 r4                 ;!/* 0100nnnn00101000 shll16 &lt;REG_N&gt;      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
	shll2 r4                  ;!/* 0100nnnn00001000 shll2 &lt;REG_N&gt;       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
	shll8 r4                  ;!/* 0100nnnn00011000 shll8 &lt;REG_N&gt;       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
	shlr r4                   ;!/* 0100nnnn00000001 shlr &lt;REG_N&gt;        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 &lt;REG_N&gt;      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 &lt;REG_N&gt;       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 &lt;REG_N&gt;       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,&lt;REG_N&gt;      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,&lt;REG_N&gt;     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,&lt;REG_N&gt;     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
	stc MOD,r4                ;!/* 0000nnnn01010010 stc MOD,&lt;REG_N&gt;     */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up}
	stc RE,r4                 ;!/* 0000nnnn01110010 stc RE,&lt;REG_N&gt;     */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
	stc RS,r4                 ;!/* 0000nnnn01100010 stc RS,&lt;REG_N&gt;     */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,&lt;REG_N&gt;     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,&lt;REG_N&gt;     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,&lt;REG_N&gt; */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-&lt;REG_N&gt;  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-&lt;REG_N&gt; */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
	stc.l MOD,@-r4            ;!/* 0100nnnn01010011 stc.l MOD,@-&lt;REG_N&gt; */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up}
	stc.l RE,@-r4             ;!/* 0100nnnn01110011 stc.l RE,@-&lt;REG_N&gt;  */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up}
	stc.l RS,@-r4             ;!/* 0100nnnn01100011 stc.l RS,@-&lt;REG_N&gt;  */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up}
	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-&lt;REG_N&gt; */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-&lt;REG_N&gt; */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-&lt;REG_N&gt; */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-&lt;REG_N&gt; */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,&lt;REG_N&gt;    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,&lt;REG_N&gt;    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,&lt;REG_N&gt;      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
	sts DSR,r4                ;!/* 0000nnnn01101010 sts DSR,&lt;REG_N&gt;	*/{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
	sts A0,r4                 ;!/* 0000nnnn01111010 sts A0,&lt;REG_N&gt;	*/{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
	sts X0,r4                 ;!/* 0000nnnn10001010 sts X0,&lt;REG_N&gt;	*/{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
	sts X1,r4                 ;!/* 0000nnnn10011010 sts X1,&lt;REG_N&gt;	*/{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
	sts Y0,r4                 ;!/* 0000nnnn10101010 sts Y0,&lt;REG_N&gt;	*/{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
	sts Y1,r4                 ;!/* 0000nnnn10111010 sts Y1,&lt;REG_N&gt;	*/{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-&lt;REG_N&gt;*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-&lt;REG_N&gt;*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-&lt;REG_N&gt;  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
	sts.l DSR,@-r4            ;!/* 0100nnnn01100110 sts.l DSR,@-&lt;REG_N&gt;	*/{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
	sts.l A0,@-r4             ;!/* 0100nnnn01110110 sts.l A0,@-&lt;REG_N&gt;	*/{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
	sts.l X0,@-r4             ;!/* 0100nnnn10000110 sts.l X0,@-&lt;REG_N&gt;	*/{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up}
	sts.l X1,@-r4             ;!/* 0100nnnn10010110 sts.l X1,@-&lt;REG_N&gt;	*/{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up}
	sts.l Y0,@-r4             ;!/* 0100nnnn10100110 sts.l Y0,@-&lt;REG_N&gt;	*/{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up}
	sts.l Y1,@-r4             ;!/* 0100nnnn10110110 sts.l Y1,@-&lt;REG_N&gt;	*/{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}
	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub &lt;REG_M&gt;,&lt;REG_N&gt; */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc &lt;REG_M&gt;,&lt;REG_N&gt;*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv &lt;REG_M&gt;,&lt;REG_N&gt;*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b &lt;REG_M&gt;,&lt;REG_N&gt;*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w &lt;REG_M&gt;,&lt;REG_N&gt;*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @&lt;REG_N&gt;      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
	trapa #4                  ;!/* 11000011i8*1.... trapa #&lt;imm&gt;        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
	tst #4,R0                 ;!/* 11001000i8*1.... tst #&lt;imm&gt;,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst &lt;REG_M&gt;,&lt;REG_N&gt; */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #&lt;imm&gt;,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
	xor #4,R0                 ;!/* 11001010i8*1.... xor #&lt;imm&gt;,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor &lt;REG_M&gt;,&lt;REG_N&gt; */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #&lt;imm&gt;,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct &lt;REG_M&gt;,&lt;REG_N&gt;*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
	dt r4                     ;!/* 0100nnnn00010000 dt &lt;REG_N&gt;          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l &lt;REG_M&gt;,&lt;REG_N&gt;*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l &lt;REG_M&gt;,&lt;REG_N&gt;*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @&lt;REG_M&gt;+,@&lt;REG_N&gt;+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
	braf r4                   ;!/* 0000nnnn00100011 braf &lt;REG_N&gt;       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
	bsrf r4                   ;!/* 0000nnnn00000011 bsrf &lt;REG_N&gt;       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
	movs.w @-r4,a1            ;!/* 111101nnmmmm0000 movs.w @-&lt;REG_N&gt;,&lt;DSP_REG_M&gt; */   {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up}
	movs.w @r4,a1             ;!/* 111101nnmmmm0001 movs.w @&lt;REG_N&gt;,&lt;DSP_REG_M&gt; */    {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up}
	movs.w @r4+,a1            ;!/* 111101nnmmmm0010 movs.w @&lt;REG_N&gt;+,&lt;DSP_REG_M&gt; */   {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up}
	movs.w @r4+r8,a1          ;!/* 111101nnmmmm0011 movs.w @&lt;REG_N&gt;+r8,&lt;DSP_REG_M&gt; */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}
	movs.w a1,@-r4            ;!/* 111101nnmmmm0100 movs.w &lt;DSP_REG_M&gt;,@-&lt;REG_N&gt; */   {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up}
	movs.w a1,@r4             ;!/* 111101nnmmmm0101 movs.w &lt;DSP_REG_M&gt;,@&lt;REG_N&gt; */    {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up}
	movs.w a1,@r4+            ;!/* 111101nnmmmm0110 movs.w &lt;DSP_REG_M&gt;,@&lt;REG_N&gt;+ */   {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up}
	movs.w a1,@r4+r8          ;!/* 111101nnmmmm0111 movs.w &lt;DSP_REG_M&gt;,@&lt;REG_N&gt;+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}
	movs.l @-r4,a1            ;!/* 111101nnmmmm1000 movs.l @-&lt;REG_N&gt;,&lt;DSP_REG_M&gt; */   {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up}
	movs.l @r4,a1             ;!/* 111101nnmmmm1001 movs.l @&lt;REG_N&gt;,&lt;DSP_REG_M&gt; */    {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up}
	movs.l @r4+,a1            ;!/* 111101nnmmmm1010 movs.l @&lt;REG_N&gt;+,&lt;DSP_REG_M&gt; */   {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up}
	movs.l @r4+r8,a1          ;!/* 111101nnmmmm1011 movs.l @&lt;REG_N&gt;+r8,&lt;DSP_REG_M&gt; */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}
	movs.l a1,@-r4            ;!/* 111101nnmmmm1100 movs.l &lt;DSP_REG_M&gt;,@-&lt;REG_N&gt; */   {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up}
	movs.l a1,@r4             ;!/* 111101nnmmmm1101 movs.l &lt;DSP_REG_M&gt;,@&lt;REG_N&gt; */    {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up}
	movs.l a1,@r4+            ;!/* 111101nnmmmm1110 movs.l &lt;DSP_REG_M&gt;,@&lt;REG_N&gt;+ */   {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up}
	movs.l a1,@r4+r8          ;!/* 111101nnmmmm1111 movs.l &lt;DSP_REG_M&gt;,@&lt;REG_N&gt;+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}
	nopx                      ;!/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up}
	nopy                      ;!/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up}
	movx.w @r4,x1             ;!/* n*m*0*01** movx.w @&lt;REG_N&gt;,&lt;DSP_REG_X&gt; */    {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}
	movx.w @r4+,x1            ;!/* n*m*0*10** movx.w @&lt;REG_N&gt;+,&lt;DSP_REG_X&gt; */   {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}
	movx.w @r4+r8,x1          ;!/* n*m*0*11** movx.w @&lt;REG_N&gt;+r8,&lt;DSP_REG_X&gt; */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}
	movx.w a1,@r4             ;!/* n*m*1*01** movx.w &lt;DSP_REG_M&gt;,@&lt;REG_N&gt; */    {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}
	movx.w a1,@r4+            ;!/* n*m*1*10** movx.w &lt;DSP_REG_M&gt;,@&lt;REG_N&gt;+ */   {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}
	movx.w a1,@r4+r8          ;!/* n*m*1*11** movx.w &lt;DSP_REG_M&gt;,@&lt;REG_N&gt;+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}
	movy.w @r6,y0             ;!/* *n*m*0**01 movy.w @&lt;REG_N&gt;,&lt;DSP_REG_Y&gt; */    {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}
	movy.w @r6+,y0            ;!/* *n*m*0**10 movy.w @&lt;REG_N&gt;+,&lt;DSP_REG_Y&gt; */   {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}
	movy.w @r6+r9,y0          ;!/* *n*m*0**11 movy.w @&lt;REG_N&gt;+r9,&lt;DSP_REG_Y&gt; */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}
	movy.w a1,@r6             ;!/* *n*m*1**01 movy.w &lt;DSP_REG_M&gt;,@&lt;REG_N&gt; */    {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}
	movy.w a1,@r6+            ;!/* *n*m*1**10 movy.w &lt;DSP_REG_M&gt;,@&lt;REG_N&gt;+ */   {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}
	movy.w a1,@r6+r9          ;!/* *n*m*1**11 movy.w &lt;DSP_REG_M&gt;,@&lt;REG_N&gt;+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}
	pmuls x0,y0,m0            ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up}
	psubc x1,y0,m0            ;!/* 10100000xxyynnnn psubc &lt;DSP_REG_X&gt;,&lt;DSP_REG_Y&gt;,&lt;DSP_REG_N&gt; */  {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up}
	paddc x1,y0,m0            ;!/* 10110000xxyynnnn paddc &lt;DSP_REG_X&gt;,&lt;DSP_REG_Y&gt;,&lt;DSP_REG_N&gt; */  {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up}
	pcmp x1,y0                ;!/* 10000100xxyynnnn pcmp &lt;DSP_REG_X&gt;,&lt;DSP_REG_Y&gt; */  {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up}
	pwsb x1,y0,m0             ;!/* 10100100xxyynnnn pwsb &lt;DSP_REG_X&gt;,&lt;DSP_REG_Y&gt;,&lt;DSP_REG_N&gt; */  {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up}
	pwad x1,y0,m0             ;!/* 10110100xxyynnnn pwad &lt;DSP_REG_X&gt;,&lt;DSP_REG_Y&gt;,&lt;DSP_REG_N&gt; */  {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up}
	pabs x1,m0                ;!/* 10001000xxyynnnn pabs &lt;DSP_REG_X&gt;,&lt;DSP_REG_N&gt; */  {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up}
	pabs y0,m0                ;!/* 10101000xxyynnnn pabs &lt;DSP_REG_Y&gt;,&lt;DSP_REG_N&gt; */  {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up}
	prnd x1,m0                ;!/* 10011000xxyynnnn prnd &lt;DSP_REG_X&gt;,&lt;DSP_REG_N&gt; */  {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up}
	prnd y0,m0                ;!/* 10111000xxyynnnn prnd &lt;DSP_REG_Y&gt;,&lt;DSP_REG_N&gt; */  {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up}
	dct pshl x1,y0,m0         ;!/* 10000001xxyynnnn pshl &lt;DSP_REG_X&gt;,&lt;DSP_REG_Y&gt;,&lt;DSP_REG_N&gt; */  {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up}
	pshl #4,m0                ;!/* 00000iiiiiiinnnn pshl #&lt;imm&gt;,&lt;DSP_REG_N&gt; */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up}
	dct psha x1,y0,m0         ;!/* 10010001xxyynnnn psha &lt;DSP_REG_X&gt;,&lt;DSP_REG_Y&gt;,&lt;DSP_REG_N&gt; */  {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up}
	psha #4,m0                ;!/* 00010iiiiiiinnnn psha #&lt;imm&gt;,&lt;DSP_REG_N&gt; */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up}
	dct psub x1,y0,m0         ;!/* 10100001xxyynnnn psub &lt;DSP_REG_X&gt;,&lt;DSP_REG_Y&gt;,&lt;DSP_REG_N&gt; */  {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up}
	dct padd x1,y0,m0         ;!/* 10110001xxyynnnn padd &lt;DSP_REG_X&gt;,&lt;DSP_REG_Y&gt;,&lt;DSP_REG_N&gt; */  {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up}
	dct pand x1,y0,m0         ;!/* 10010101xxyynnnn pand &lt;DSP_REG_X&gt;,&lt;DSP_REG_Y&gt;,&lt;DSP_REG_N&gt; */  {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up}
	dct pxor x1,y0,m0         ;!/* 10100101xxyynnnn pxor &lt;DSP_REG_X&gt;,&lt;DSP_REG_Y&gt;,&lt;DSP_REG_N&gt; */  {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up}
	dct por  x1,y0,m0         ;!/* 10110101xxyynnnn por  &lt;DSP_REG_X&gt;,&lt;DSP_REG_Y&gt;,&lt;DSP_REG_N&gt; */  {"por",  {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up}
	dct pdec x1,m0            ;!/* 10001001xxyynnnn pdec &lt;DSP_REG_X&gt;,&lt;DSP_REG_N&gt; */  {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up}
	dct pdec y0,m0            ;!/* 10101001xxyynnnn pdec &lt;DSP_REG_Y&gt;,&lt;DSP_REG_N&gt; */  {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up}
	dct pinc x1,m0            ;!/* 10011001xx00nnnn pinc &lt;DSP_REG_X&gt;,&lt;DSP_REG_N&gt; */  {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up}
	dct pinc y0,m0            ;!/* 1011100100yynnnn pinc &lt;DSP_REG_Y&gt;,&lt;DSP_REG_N&gt; */  {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up}
	dct pclr m0               ;!/* 10001101xxyynnnn pclr &lt;DSP_REG_N&gt; */  {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up}
	dct pdmsb x1,m0           ;!/* 10011101xx00nnnn pdmsb &lt;DSP_REG_X&gt;,&lt;DSP_REG_N&gt; */  {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up}
	dct pdmsb y0,m0           ;!/* 1011110100yynnnn pdmsb &lt;DSP_REG_Y&gt;,&lt;DSP_REG_N&gt; */  {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up}
	dct pneg  x1,m0           ;!/* 11001001xxyynnnn pneg  &lt;DSP_REG_X&gt;,&lt;DSP_REG_N&gt; */  {"pneg",  {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up}
	dct pneg  y0,m0           ;!/* 11101001xxyynnnn pneg  &lt;DSP_REG_Y&gt;,&lt;DSP_REG_N&gt; */  {"pneg",  {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up}
	dct pcopy x1,m0           ;!/* 11011001xxyynnnn pcopy &lt;DSP_REG_X&gt;,&lt;DSP_REG_N&gt; */  {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up}
	dct pcopy y0,m0           ;!/* 11111001xxyynnnn pcopy &lt;DSP_REG_Y&gt;,&lt;DSP_REG_N&gt; */  {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up}
	dct psts MACH,m0          ;!/* 11001101xxyynnnn psts MACH,&lt;DSP_REG_N&gt; */  {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up}
	dct psts MACL,m0          ;!/* 11011101xxyynnnn psts MACL,&lt;DSP_REG_N&gt; */  {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up}
	dct plds m0,MACH          ;!/* 11101101xxyynnnn plds &lt;DSP_REG_N&gt;,MACH */  {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up}
	dct plds m0,MACL          ;!/* 11111101xxyynnnn plds &lt;DSP_REG_N&gt;,MACL */  {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}
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